The present invention relates to a semiconductor integrated circuit device and the method of controlling the same.
An EEPROM (electrically erasable programmable read-only memory), one of different kinds of nonvolatile memories, has a plurality of memory cells. A known memory Ad cell consists of a floating gate field effect transistor (FET) with a double-layer electrode structure composed of a source region, a drain region, a channel region, a floating gate electrode provided on the channel region via an insulating film, and a control gate electrode provided on the floating gate electrode via an insulating film. A control signal is sent to the control gate electrode via a word line. As a structure of the word line, a structure constituted by a main word line and a sub word line connected to the main word line via a switching element is known. Such a structure is employed in a conventional flash memory, in which a large amount of currents flow into memory cells during a read or write operation. This is because, when a structure composed of a bit line and a sub bit line is employed in the flash memory, a voltage across the switching element for connecting the main bit line and the sub bit line falls markedly and this may result in misreading of the memory cells or an increased load on a circuit for generating a write voltage.
The flash memory has a plurality of memory blocks with memory cells arranged in a matrix therein. Each of the memory blocks is provided with a bit line decoder and bit lines, independently of the other memory blocks. Information is read from the flash memory having such a configuration as follows.
First, a switching element connecting a main word line and a sub word line is turned on to select the main word line and the sub word line, and then a voltage required for a read operation is applied to the sub word line through the main word line. Subsequently, a predetermined voltage is applied to a selected bit line to select a memory cell. Then, a current flowing through the selected memory cell is compared with a predetermined reference value by a differential amplifier, and a result determined based on the comparison is output as data.
At this time, when a charge remains in drains of unselected memory cells commonly connected to the sub word line, that is, memory cells for which the associated word line is selected and of which the sources have a low potential, the charge accumulated in the drain is pulled out, or extracted to the source side. In the flash memory, since memory cells in the same memory block usually have their sources commonly connected, currents to the sources in these unselected memory cells raise a source potential and may result in misreading.
Furthermore, since the charge in the drain is pulled to the source side in the unselected memory cells, hot electrons, that is, high-energy electrons are generated, and the electrons are injected into the floating gate electrodes of the unselected memory cells. Therefore, the threshold value of the unselected memory cells may rise.
Therefore, in general, the bit lines connected to the drains of the memory cells are connected to a discharge circuit via a switching element so that the charge in the drains of the memory cells is extracted via the bit lines when the flash memory is in a standby state, that is, a non-access state.
Meanwhile, in the conventional flash memory, when electrons are extracted from a floating gate electrode of a memory cell (an erase operation is assumed here), a method of applying a negative voltage to a word line is employed in general. In this case, the following problems occur in a flash memory having main word lines and sub word lines, the latter being provided in each memory block independently of the other memory blocks.
The switching element connecting the main word line and the sub word line needs to transmit a positive voltage during read and write operations and a negative voltage during an erase operation. Therefore, voltage control of the switching element becomes complicated and a control circuit provided to apply the positive voltage and the negative voltage to the switching element disadvantageously enlarges the memory.
An example of a semiconductor integrated circuit device having main word lines and sub word lines like the above-described flash memory is shown in FIG. 5. The semiconductor integrated circuit device has a memory cell region M made up of a plurality of memory blocks MB0, . . . , MBX and main word lines WLM0, . . . , WLMn commonly connected to the plurality of memory block MB0, . . . , MBX. Each memory block MB0, . . . , MBX has a plurality of memory cells MC00, . . . , MCnm arranged in a matrix. Each memory cell MC00, . . . , MCnm, consists of a floating gate type field effect transistor having a control electrode and a floating electrode. Furthermore, in each of the memory blocks MB0, . . . , MBX, drain regions of the memory cells in the same column are commonly connected by an associated bit line BL0, . . . , or BLm, while control gate electrodes of the memory cells in the same row are commonly connected by a sub word line WLS0, . . . , or WLSn. Furthermore, P-type MOS (Metal Oxide Semiconductor) field effect transistors LWS00, . . . , LWSXn for selecting sub word lines WLS0, . . . , WLSn are provided in each of the memory blocks MB0, . . . , MBX. The P-type MOS field effect transistors LWS00, . . . , LWSXn of each memory block are connected to a sub word line selecting circuit 100 via an associated memory block selecting gate line BS0, . . . , or BSX and to a voltage switching circuit 200 for switching between a back bias high voltage and a voltage VSS via an associated back bias supply line NW0, . . . , or NWX. Furthermore, to pull out a charge accumulated in the bit line BL0, . . . , BLm, the bit line BL0, . . . , BLm is grounded via a MOS field effect transistor DC0, . . . , DCm. The MOS field effect transistor DC0, . . . , DCm is controlled by a discharge selecting gate line DDC0, . . . , DDCm. Furthermore, the main word line WLM0, . . . , WLMn and the sub word line WLS0, . . . , WLSn are connected via the P-type MOS field effect transistor LWS00, . . . , LWSXn. A voltage is supplied from a main word line decoder MWD to the main word line WLM0, . . . , WLMn. Furthermore, in the sub word line selecting circuit 100 from which a voltage is supplied to a P-type MOS field effect transistor LWS00, . . . , LWSXn, control for generating a negative voltage required depending on the operation is performed. As is obvious, since the field effect transistors DC0, . . . , DCm, the sub word line selecting circuit 100 and the voltage switching circuit 200 are required in each memory block MB0, . . . , MBX, the circuit size becomes large.
Hereafter, voltage control during a read operation in the semiconductor integrated circuit device will be explained below with reference to FIG. 6. In FIG. 6, it is assumed that a memory cell MC00 in the memory block MB0 is selected.
In a read operation, as shown in FIG. 6, a voltage of about 5 V is applied to the control gate electrode of the memory cell MC00, while a voltage of about 1 V is applied to the drain region of the memory cell MC00. At this time, a voltage to be applied to the control gate electrodes of unselected memory cells MC10, . . . , MC1m; . . . ; MCn0, . . . , MCnm in the memory block MB0 needs to be set at 0 V. Therefore, a voltage of xe2x88x925 V is applied to the memory block selecting gate line BS0, and the main word lines WLM1xe2x88x92WLMn at 0 V are electrically connected to the associated sub word line WLS1xe2x88x92WLSn.
Voltage control during a write operation in the semiconductor integrated circuit device is explained below with reference to FIG. 7. In FIG. 7, it is assumed that a memory cell MC00 in the memory block MB0 is selected.
During a write operation, as shown in FIG. 7, a voltage of about 10 V is applied to the control gate electrode of the memory cell MC00, while a voltage of 4 to 5 V is applied to the drain region of the memory cell MC00. At this time, a voltage to be applied to the control gate electrodes of unselected memory cells MC10, . . . , MC1m; . . . ; MCn0, . . . , MCnm in the memory block MB0 needs to be set at 0 V. Therefore, a voltage of the memory block selecting gate line BS0 must be a negative voltage. Furthermore, a voltage of 10 V must not be applied to the sub word lines WLS0, . . . , WLSn in the unselected memory blocks MB1, . . . , MBX so that write reliability is ensured. That is, the voltage of the control gate electrodes of the memory cells MC00, . . . , MCnm in the unselected memory blocks MB1, . . . , MBX needs to be 0 V. Therefore, a voltage of about 10 V is applied to the gate electrodes of the P-type MOS field effect transistors LWS10xe2x80x94LWSxn in the unselected memory blocks MB1, . . . , MBX. Meanwhile, when a voltage of about xe2x88x925 V similar to that of the read operation is applied to the gate electrode of the P-type MOS field effect transistor LWS00, . . . , LWS0n in the selected memory block MB0, a voltage across the source and gate electrode of the P-type MOS field effect transistor LWS00 exceeds the withstand or breakdown voltage, and the P-type MOS field effect transistor LWS00 may be damaged. Therefore, during the write operation, the gate voltage of the P-type MOS field effect transistor LWS00, . . . , LWS0n in the selected memory block MB0 is generally set at a voltage smaller than that of the read operation, for example, xe2x88x922 V.
As described above, in the case of a semiconductor integrated circuit device having main word lines WLM0, . . . , WLMn and sub word lines WLS0, . . . , WLSn, voltage control of gate electrodes of switching elements LWS00, . . . , LWSXn or the like is essential during each of read and write operations. Therefore, a back bias control circuit of switching elements LWS00, . . . , LWSXn selecting the sub word lines WLS0, . . . , WLSn and a circuit for controlling gate voltages of switching elements LWS00, . . . , LWSXn are required. As a result, the control circuit becomes complicated and the peripheral circuit is enlarged, which may result in a larger chip size.
Meanwhile, with recent development in fine processing technology, a lower operating current for a memory cell has been achieved. Consequently, memory array configuration having main bit lines and sub bit lines has become employable in a semiconductor integrated circuit device. Since each memory block has word lines independently of the other memory blocks in the semiconductor integrated circuit device having main bit lines and sub bit lines, the switching elements requiring complicated voltage control become unnecessary. Furthermore, since the wiring capacitance of the word line is decreased, time required for reading or writing data from/to the memory cell can be shortened.
However, even in the semiconductor integrated circuit device having main bit lines and sub bit lines, a switching element for extracting a charge accumulated in the drain region of the memory cell at the time of standby (at the time of non-access) needs to be disposed in each memory block. As a result, a circuit for controlling the switching element is required in each memory block, and thus a problem arises that the circuit size is increased.
Examples of the semiconductor integrated circuit device having main bit lines and sub bit lines described above include the one disclosed in Japanese Patent Laid-Open Publication No. 9-153559. The semiconductor integrated circuit device described in this Japanese Patent Laid-Open Publication is provided with elements for pulling a charge accumulated in the drain regions of memory cells without passing through the memory cells and has a path for eliminating the charge. However, according to the semiconductor integrated circuit device of the Japanese Patent Laid-Open Publication No. 9-153559, since the elements for pulling the charge and a circuit for controlling the elements are provided in each of a plurality of memory blocks, a problem arises that a circuit occupation area around the memory block is increased.
Accordingly, the object of the present invention is to provide a semiconductor integrated circuit device which is allowed to have a reduced circuit occupation area, and a method of controlling the same.
A semiconductor integrated circuit device according to the present invention includes a plurality of memory blocks. Each memory block includes:
a plurality of nonvolatile memory cells arranged in a matrix form, each nonvolatile memory cell having a gate region, a source region and a drain region;
word lines each of which is commonly connected to the gate regions of the nonvolatile memory cells in the same row;
a source line which is commonly connected to the source regions of the nonvolatile memory cells;
sub bit lines each of which is commonly connected to the drain regions of the nonvolatile memory cells in the same column; and
first switching elements for selecting the associated sub bit lines,
The plurality of memory blocks being arranged in a column direction, and the semiconductor integrated circuit device further includes:
main bit lines which are common to the plurality of memory blocks and to which the sub bit lines in each memory block are connected via the respective first switching elements; and
at least one second switching element for extracting charges accumulated in drain regions of the nonvolatile memory cells via the first switching elements and the main bit lines.
According to the semiconductor integrated circuit device having the above configuration, when the first and second switching elements are turned on, charges accumulated in the drain regions of the nonvolatile memory cells are extracted or pulled out via the first switching elements and the main bit line. Since the charges in the drain regions of the nonvolatile memory cells are extracted therefrom via the first switching elements and the main bit lines, no switching elements for extracting the charges from the drain regions of the nonvolatile memory cells need to be provided on the sub bit lines. That is, no second switching elements for extracting the charges need to be provided in each memory block. Therefore, no circuits for controlling the second switching elements for extracting the charges need to be provided for each memory block, either. Thus the circuit occupation area of the semiconductor integrated circuit device of the present invention can be reduced.
Furthermore, because each of the main bit lines is commonly used by the plurality of memory blocks, control for extracting charges does not need to be performed in each memory block. Therefore, the control for extracting the charges from the drain regions of the nonvolatile memory cells is simplified.
Each memory cell may be constituted of a floating gate type field effect transistor.
In one embodiment, one second switching element is provided for one main bit line. Thus, a charge can be extracted every main bit line by controlling the second switching elements.
In one embodiment, the main bit lines are grounded via the at least one second switching element. Thus, the charge accumulated in the drain region of the nonvolatile memory cell can be allowed to escape to the ground.
The first switching elements in one memory block may be connected to a common signal line.
In one embodiment, each of the first switching elements is constituted of a MOS field effect transistor through which the sub bit lines are connected to the associated bit lines. Also, the gates of the MOS field effect transistors in one memory block are commonly connected to a memory block selecting gate line.
The present invention also provides a method of controlling the semiconductor integrated circuit device with the above arrangement. In the controlling method, upon completion of at least one of read, write and erase operations of selected nonvolatile memory cells in the memory blocks, the first switching elements and the at least one second switching element are turned on.
With this controlling method, occurrence of hot electrons can be prevented by extracting the charges in the drain regions of the nonvolatile memory cells via the first switching elements, the main bit lines and the at least one second switching element.
The present invention provides another method of controlling the semiconductor integrated circuit device with the above arrangement. In this controlling method, upon completion of each of read, write and erase operations of selected nonvolatile memory cells in the memory blocks, the first switching elements are turned on.
According to this controlling method, since the first switching elements are in an on state before and after the read, write and erase operations of the selected nonvolatile memory cells in the memory blocks, charges in the drain regions of the nonvolatile memory cells are extracted only by turning on the second switching element. Therefore, control for extracting the charges before and after the read, write and erase operations of the selected nonvolatile memory cells is simplified.
Furthermore, the present invention provides a still another method of controlling the semiconductor integrated circuit device with the above configuration. In the controlling method, the first switching elements and the at least one second switching element are turned on in a standby state of the device to thereby extract charges accumulated in the drain regions of the nonvolatile memory cells.
With this controlling method, occurrence of hot electrons after the device is released from the standby state can be prevented.
Other objects, features and advantages of the present invention will be obvious from the following description.